C4 (Controlled Collapse Chip Connection) interconnect reliability is a critical factor for product reliability for chips on organic substrates. However, C4s have been known to fail under certain situations. One failure mode for C4 reliability is solder fatigue due to the thermal mismatch between a chip and a laminate. For example, Pb-free C4s, when used with flipped chip plastic ball grid array (FCPBGA) organic laminate packaging, tend to transfer coefficient of thermal expansion (CTE) mismatch stresses to the underlying chip-level back end of line (BEOL). This can result in dielectric cracking and structural damage, creating a reliability risk. This chip-package interaction (CPI) issue is an emerging reliability problem being faced by integrated circuit manufacturers today.
A second failure mode affecting C4 reliability is caused by the migration to lead-free solders, which causes “white bumps.” “White bumps” is a term that refers to the issue of chip cracking due to translation of vertical stresses during chip join or other thermal processing after the chip is joined to the organic laminate, in a package. More specifically, “white bumps” are a tearout of the chip BEOL metallization due to the stress that is caused by CTE mismatch between the Si chip and the organic carrier during thermal cycling. It has been found that this tearout occurs during the cooldown of the chip join reflow, where the C4 rigidly connects the chip to the carrier. White bumps present a reliability concern as the structure containing the white bumps may or may not test as electrical “open.”
As an example, with larger chip sizes and organic laminate FCPBGA packages, CTE mismatch between the laminate and chip creates stresses during thermal processing that can result in chip-level cracking and film delamination. One failure mechanism is related to shear stresses at individual C4 bump sites during chip-attach processing that in turn give rise to tensile stresses of sufficient magnitude to induce cohesive or adhesive film failure directly beneath the solder ball. If the stress is allowed to exceed the strength of the chip BEOL, damage in the chip will occur. Illustratively, module level stresses may induce chip-level BEOL cracking beneath the Pb-free C4 interconnect. Once initiated, cracks can propagate laterally through proximal BEOL structures causing the “white-bumps” failure mode.
The white bump problem is particularly serious with Pb-free C4 technology, due to the stiffness of the Pb-free bump. Moreover, the white bump problem may affect corner C4's in particular. Additionally, the white bump problem is exacerbated for smaller C4's (for example with a <=150 μm pitch) due to lower chip standoff.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.